There is a pipeline A/D converter as an example of a high-speed and high-precision A/D converter. The pipeline A/D converter has a plurality of conversion stages connected in cascade, and the first conversion stage outputs a highest-order digit of a digital output signal while the second and subsequent stages successively perform pipeline operations to output lower-order digits. Each of the conversion stages has a sub A/D converter and a MDAC (Multiplying D/A Converter).
In order to realize speed-up of the pipeline A/D converter, speed-up and high precision of an operational amplifier used for the MDAC in each conversion stage are required. However, in realizing speed-up of the operational amplifier, power consumption is significantly increased, and such speed-up has a limitation, leading to a bottleneck in speed-up of the A/D converter.
In order to realize speed-up of the pipeline A/D converter, Non-Patent Document 1 discloses that a line of cascade-connected conversion stages is regarded as a unit A/D converter, and a plurality of unit A/D converters are arranged in parallel to each other to perform A/D conversions in parallel and time-divisionally, thereby to achieve speed-up.
The operational amplifier in the conversion stage of the pipeline A/D converter is in its active state and its reset state alternately for each half clock period during the conversion processing. Utilizing this effect, Non-Patent Document 2 provides an A/D converter which time-divisionally performs parallel processings by using a plurality of unit A/D converters, in which parallel-arranged conversion stages in adjacent unit A/D converters time-divisionally share an operational amplifier for each half clock, thereby to realize low power consumption.    Non-Patent Document 1: Arias, J; Boccuzzi, V.; Quintanilla, L.; Enriquez, L.; Bisbal, D.; Banu, M.; Barbolla, J., “Low-power pipeline ADC for wireless LANs”, IEEE Journal of Solid-State Circuits, Volume 39, Issue 8, August 2004, pp. 1338-1340    Non-Patent Document 2: Conroy, C. S. G; Cline, D. W.; Gray, P. R., “An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS”, IEEE Journal of Solid-State Circuits, Volume 28, Issue 4, April 1993, pp. 447-454